Title:
RELATIVE VARIATION REDUCTION LAYOUT
Document Type and Number:
Japanese Patent JP2006101108
Kind Code:
A
Abstract:
To reduce the deviation of two-line output by the relative variation in a semiconductor integrated circuit, such as a differential amplifier circuit, etc.
The semiconductor integrated circuit constituted by differential transistor pairs, such as the differential amplifier, etc., includes at least one conduction type region, and includes a plurality of bipolar transistors which share the conduction type region as a collector region. The plurality of the bipolar transistors share each base electrode terminal mutually. The plurality of the bipolar transistors share each emitter electrode terminal mutually. The plurality of the bipolar transistors have a layout where each collector electrode terminal is provided independently.
Inventors:
MIYAWAKI DAISUKE
KOMORI HIROSHI
KOMORI HIROSHI
Application Number:
JP2004283876A
Publication Date:
April 13, 2006
Filing Date:
September 29, 2004
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03F3/45
Attorney, Agent or Firm:
Fumio Iwahashi
Tomoyasu Sakaguchi
Hiroki Naito
Tomoyasu Sakaguchi
Hiroki Naito
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