Title:
弛張発振回路
Document Type and Number:
Japanese Patent JP5456736
Kind Code:
B2
Abstract:
A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.
Inventors:
Seiichiro Shiga
Tetsuya Hirose
Large saki
Tetsuya Hirose
Large saki
Application Number:
JP2011185043A
Publication Date:
April 02, 2014
Filing Date:
August 26, 2011
Export Citation:
Assignee:
Semiconductor Science and Engineering Research Center Co., Ltd.
International Classes:
H03K3/0231; H03K3/354; H03K4/08
Domestic Patent References:
JP2001203563A |
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Kawabata Junichi
Mitsuo Tanaka
Kawabata Junichi
Previous Patent: JPS5456735
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