Title:
RELAY SUBSTRATE FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR SUB PACKAGE AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3842272
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To permit easy guarantee of the KGD (Known-Good-Die) of respective semiconductor chips to enable the manufacture of a semiconductor device under a high factor of non-defective unit and permit the utilization of the position, pitch, signal arrangement or the like of terminals of respective semiconductor chips as they are without restraining them, upon constituting one set of packaged semiconductor device by incorporating a plurality of semiconductor chips thereinto.
SOLUTION: A projection provided on a semiconductor chip mount sealing sub substrate 100 is bonded onto the package substrate 10. Semiconductor bear chips 31, 32 are arranged in a space formed between the semiconductor chip mount sealing sub substrate 100 and the package substrate 10 to permit wiring.
Inventors:
Nakajima Moriyoshi
Kazuo Kobayashi
Mika Natsuo
Kazuo Kobayashi
Mika Natsuo
Application Number:
JP2004164489A
Publication Date:
November 08, 2006
Filing Date:
June 02, 2004
Export Citation:
Assignee:
Genusion Co., Ltd.
International Classes:
H01L23/29; H01L25/18; H01L23/31; H01L25/065; H01L25/07; (IPC1-7): H01L25/065; H01L23/29; H01L23/31; H01L25/07; H01L25/18
Domestic Patent References:
| JP2002334966A | ||||
| JP2002093937A | ||||
| JP11017057A | ||||
| JP2002040095A | ||||
| JP2003100985A | ||||
| JP5343608A | ||||
| JP2004022664A |
Attorney, Agent or Firm:
Hisao Komori
Tatsuichi Murakami
Tatsuichi Murakami
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