Title:
REMOVAL FILTER
Document Type and Number:
Japanese Patent JPS61276411
Kind Code:
A
Abstract:
A decimating filter utilizing first and second switched input capacitors for sampling an input signal on opposite phases of a first sampling clock signal. The switched input capacitors are connected to an integrating circuit for filtering the sampling signal. An output of the integrating circuit is sampled according to a second sampling clock signal having a frequency equal to a submultiple of the first sampling clock signal frequency. By sampling the input signal on opposite phases, the input signal is effectively sampled at twice the first sampling clock signal frequency. Accordingly, in applications involving high sampling frequencies, such as digital signal transmission, the input signal can be sampled at a sufficiently high frequency without requiring a prohibitively high input sampling clock frequency. The decimating filter is of simple design and can be inexpensively implemented on an integrated circuit chip requiring small area.
Inventors:
ROJIYAA KORUBETSUKU
PIITAA GIRINGUHAMU
PIITAA GIRINGUHAMU
Application Number:
JP12204386A
Publication Date:
December 06, 1986
Filing Date:
May 26, 1986
Export Citation:
Assignee:
MITEL CORP
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Domestic Patent References:
| JPS57106216A | 1982-07-02 |
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)
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