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Title:
REPEATING CYCLE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS631976
Kind Code:
A
Abstract:

PURPOSE: To reduce the effect of change with time and to prevent the erroneous operation of a shift register due to noise, by determining a predetermined measuring range of a repeating cycle on the basis of the number of reference pulses.

CONSTITUTION: A shift register 10, FF 20 and a reference pulse generator 30 are provided to a repeating cycle detection circuit and the output of the m-th stage of the register 10 is applied to the input D of FF 20. The output of the n-th stage (m<n) of the register 1 is applied to the reset terminal R of FF 20 and the reference pulse from the generator 30 is inputted to the clock terminal CK of FF of each stage of the register 10. Further, a signal to be measured being a repeating signal of a definite cycle is inputted to the reset terminal R of FF of each stage of the register 10 and the clock terminal CK of FF 20. Then, a predetermined measuring range of a repeating cycle is determined on the basis of the number of reference pulses and the effect of change with time is reduced and the erroneous operation of the shift register due to noise is prevented.


Inventors:
TANIDO YOSHIAKI
Application Number:
JP14588586A
Publication Date:
January 06, 1988
Filing Date:
June 20, 1986
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K5/19; G01R23/10; G01R23/15; G06F11/30; H03K5/153; (IPC1-7): G01R23/15; G06F11/30; H03K5/153
Attorney, Agent or Firm:
Sadaichi Igita



 
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