PURPOSE: To prevent an erroneous detection at the time of detecting leading synchronizing signals and also to obtain a correct synchronization even when an error is generated in the leading synchronizing signal in the case of reproducing digital information signal.
CONSTITUTION: The erroneous detection is prevented by providing a preamble pattern detecting circuit 102 detecting preamble patterns recorded in a preamble area and by generating the detection windows of synchronization patterns by a detection window generating circuit 103 on the base of the detection timings of the preamble patterns. Further, the correct synchronization can be obtained by performing parallel conversions with a serial/parallel converting circuit 106 on the base of the detection timings.
OKAMOTO HIROO
HATANAKA YUJI
