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Patent Searching and Data


Title:
RESET CIRCUIT FOR BINARY COUNTER
Document Type and Number:
Japanese Patent JPH04235414
Kind Code:
A
Abstract:

PURPOSE: To prevent the faults occurred in the circuit performing the voltage impression operations, etc., for each output of the clock of the prescribed frequency by conventionally countering +1 extra clocks when this counter is reset by judging that the count value in the binary counter counting the clock reaches to the prescribed value.

CONSTITUTION: When the count output in the binary counter reaches to the prescribed count value by inputting the count output in a multi-input AND gate, the gate output is generated, the monostable multivibrator is triggered and the counter is reset before the next clock is generated. But the operation time in this monostable multivibrator is selected to be longer than that of the voltage impression circuit and shorter than the clock frequency.


Inventors:
YAMAMOTO HIROSHI
Application Number:
JP127491A
Publication Date:
August 24, 1992
Filing Date:
January 10, 1991
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H03K23/66; (IPC1-7): H03K23/66
Attorney, Agent or Firm:
Iwao Yamaguchi