To output an initial value of a logic circuit to be initialized to a logic circuit in the subsequent stage even in a clock-gating state.

A reset circuit, which resets a logic circuit operating in synchronization with a clock, includes an output selection unit that receives an output signal from the logic circuit and outputs any of an initial value of an output signal when the logic circuit is reset and the output signal received from the logic circuit; and a control unit that receives a reset signal for resetting the logic circuit and controls the output selection unit so that the initial value is output from the output selection unit in response to the reset signal.