Title:
RESET CIRCUIT
Document Type and Number:
Japanese Patent JPH01215120
Kind Code:
A
Abstract:
PURPOSE: To surely reset a circuit applying reset by holding the reset signal and releasing the reset signal stored at a point of time when reset is applied to a circuit to be reset.
CONSTITUTION: With a reset signal Reset given to an RS flip-flop 2, a noninverting input of the RS flip-flop 2 goes to a high level, then the output of an inverter 3 goes to a low level and each T flip-flop of a counter 4 is reset. Then all bits of the counter 4 go to a low level, and all the flip-flops of the counter 4 is reset. The output of a NOR gate 1 goes to a high level and the RS flip-flop 2 is reset and the stored reset signal Reset is released. Thus, the circuit to be reset is surely reset.
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Inventors:
SAKURAI AKINORI
Application Number:
JP4115388A
Publication Date:
August 29, 1989
Filing Date:
February 23, 1988
Export Citation:
Assignee:
NEC CORP
International Classes:
H03K21/00; H03K23/00; (IPC1-7): H03K21/00
Domestic Patent References:
JPS5031761A | 1975-03-28 |
Attorney, Agent or Firm:
Naoki Kyomoto (3 outside)