PURPOSE: To prevent malfunction of an internal LSI by turning on complementarily two MOSFETs based on an input signal so as to send the signal while eliminating chattering.

CONSTITUTION: When a level of an external reset terminal 5 is set from an L to an H after lapse of a sufficient time after application of power, a P- channel MOS TR 2 is turned off and an N-channel MOS TR 12 is turned on. As a result, a potential at a node 10 falls down quickly, an output signal of an inverter 4 goes to an H level to activate a signal fed to an internal LSI. When the level of the signal at the terminal 5 is set to an L, the FET 2 is turned on and the FET 12 is turned off. When a potential of the node 10 exceeds an input threshold level of the inverter 4, an output signal of the inverter 4 changes from H to L. Thus, the output signal of the inverter 4 responds to a rise time of an external reset signal at a high speed and to a fall time of the signal very slowly and any chattering is eliminated from an output of the inverter 4 even when the signal at the terminal 5 includes any chattering.