To normally operate a CPU after the cancel of reset by surely performing OFF processing to a flash ROM and finishing that processing to actually reset the CPU later when a reset operation is performed just while the CPU executes a processing operation to the flash ROM to take a long time for erasing processing.

When a reset switch 7 is turned on while a CPU 1 performs block erasing processing to a flash ROM 4, a reset input RSIN is inputted to an input port I of the CPU 1 and inputted to a delay circuit 8. The reset inputs are successively shifted and delayed by flip-flops consisting of the delay circuit 8 and outputted to a reset input port R of the CPU 1 as a reset output ROUT. During delay time from the reset operation to the output of the reset output ROUT, the CPU 1 performs OFF processing to the flash ROM 4 and is reset later.