To prevent an error in writing to a writable ROM in the case of a power source-off reset, to secure the normal start of a CPU and a microcomputer in the case of a power source-off reset even when operation start software exists in the ROM and to prevent the writing error even when a reset signal is generated in the case of writing in a non-volatile RAM or the writable ROM.

The reset signal generating circuit 50 supplies a first reset signal for executing an initializing operation to the CPU or the microcomputer, supplies a second reset signal to a writable ROM 30, which is more delayed than the first reset signal, and supplies a third reset signal to a non-volatile RAM 40, which is more delayed than the first reset signal. A first delay time Td1 concerning the first reset signal L when the second reset signal L is generated is longer than a third delay time Td3 concerning the first reset signal L when the third reset signal L is generated.