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Patent Searching and Data


Title:
RESET SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH06282358
Kind Code:
A
Abstract:

PURPOSE: To minimize time required for reset by allowing an output part to turn a reset signal line to the non-active side at the time of completing a reset flag state.

CONSTITUTION: A semicondictor integrated circuit (LSI) 1 receives a reset low pulse signal inputted from an external reset signal line 2 by a reset signal input part 4 to initialize its inside operation status. The input part 4 transfers control an LSI inside reset control part 6 to reset the inside of the LSI 1 and generates a reset flag setting signal to set up a flag for an LSI inside resetting part 5. Thereby an LSI inside status output part 3 is turned on. Since the output part 3 holds its ON status during the reset period of the LSI 1, the signal line 2 is fixed on a low state. When the reset flag is turned to the reset status after completing the reset of the inside, the output part 3 is turned off and an external reset signal is turned to a high level.


Inventors:
KODA KENJI
SATAKE SHOZO
Application Number:
JP6788793A
Publication Date:
October 07, 1994
Filing Date:
March 26, 1993
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICOM SYST KK
International Classes:
G06F1/24; (IPC1-7): G06F1/24
Attorney, Agent or Firm:
Ogawa Katsuo