PURPOSE: To use a reset terminal and an MPU selecting function in common by providing an external inversion gate on the input part of the reset terminal of a peripheral device.

CONSTITUTION: When a chip selecting signal CS in a control bus 17 is inputted to the terminal 23 of an input/output circuit 3, a read-out signal; the inverse of RD and a write signal; the inverse of WR are inputted to the terminals 22, 21 of the input/output circuit 3, in an 80 system MPU, and an enable signal E and a read-out/write signal R/W are inputted to the terminals 22, 21 in the same way, in a 68 system MPU, in order to control the delivery of a data to a memory 5. Also, a reset signal; the inverse of RST from an external control reset switch 6 is inputted as an MPU selection/reset signal SEL/RST to a terminal 24, as it is in case of the 80 system MPU, and through an inversion gate 16 by switching a switch 15 in case of the 68 system MPU. The inputted signals reach an internal circuit 4 as internal RD/internal WR signals 12, 13 by the SEL/RST signal.