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Patent Searching and Data


Title:
RESETTING SYSTEM OF MICROPROCESSOR CPU
Document Type and Number:
Japanese Patent JPS5896324
Kind Code:
A
Abstract:

PURPOSE: To secure resetting when a power switch is turned on at a terminal device which uses a microprocessor, by providing a monitoring control circuit which holds a voltage applied to the reset terminal of a CPU below a level L from the operation of a power switch to a rise of a CPU voltage to an operation securing voltage, or at a level H after resetting is completed.

CONSTITUTION: A terminal device which uses a microprocessor (MPU) is provided with a voltage monitoring control circuit which holds a voltage to be applied to the reset terminal of the CPU1 of the MPU below a level L from the operation of a power switch SW to a rise in CPU's voltage to an operation securing voltage, or at a level after resetting operation is completed between a power source and the reset terminal of the CPU. Consequently, when a user turns on the power switch, the resetting is secured even if chattering is generated at the contact owing to a way of operating, or in case of repetitive on-off operation.


Inventors:
JINGUU TAKASHI
YOSHIDA MITSUO
MATSUURA ATSUSHI
Application Number:
JP19297881A
Publication Date:
June 08, 1983
Filing Date:
December 02, 1981
Export Citation:
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Assignee:
NAKAYO TELECOMMUNICATIONS
NIPPON TELEGRAPH & TELEPHONE
HASEGAWA DENKI SEISAKUSHO
International Classes:
H02J1/00; G06F1/24; H03K17/22; (IPC1-7): G06F1/00