Title:
抵抗スイッチング半導体メモリー
Document Type and Number:
Japanese Patent JP2007509509
Kind Code:
A
Abstract:
One embodiment provides a non-volatile semiconductor memory with CBRAM memory cells at which there exists, between the Ag-doped GeSe layer and the Ag top electrode, a chemically inert barrier layer improving the switching properties of the CBRAM memory cell. The active matrix material layer of the memory cell includes a GeSe/Ge:H double layer with a vitreous GeSe layer and an amorphous Ge:H layer. The amorphous Ge:H layer is positioned between the GeSe layer and the second electrode. Thus, the forming of AgSe conglomerates in the Ag doping and/or electrode layer is inhibited, so that precipitations are prevented and a homogeneous deposition of the silver doping layer is enabled. By means of the GeSe/Ge:H double layer system, the resistive non-volatile storage effect of the CBRAM memory cell is, on the one hand, preserved and, on the other hand, the chemical stability of the top electrode positioned thereabove is ensured by means of the thin Ge:H layer.
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Inventors:
Woofeld, Claus Dieter
Application Number:
JP2006537324A
Publication Date:
April 12, 2007
Filing Date:
September 07, 2005
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
H01L27/105; H01L45/00
Attorney, Agent or Firm:
Kenzo Hara International Patent Office