PURPOSE: To reduce the burden of software by permitting a system to automatically transit to the state of one character one coincidence by means of hardware when a failing occurs in succession to normal state transit.

CONSTITUTION: A state transit RAM 1 outputs data D4 and D5 showing the transit state with EBC code data D1 outputted from a DMA logical part 2 as an address signal. When a failing decision circuit 9 detects failing, an AND circuit 12 outputs a control signal C3 only when a previous failing is not detected and the present failing is detected by the decided result of the failing decision circuit 9. The control signal C3 is inputted to the DMA logical part 2 and a selector 3 through an OR circuit 15 as a control signal C7. The selector 3 selects previous output data D1 of the DMA logical part 2, which is inputted through a selector 6, and inputs it to the state transit RAM 1 again. Since transit to the state of one character one coincidence can be realized by hardware, the quantity of state transit information which software sets is reduced and software itself can be simplified.