Title:
REWRITABLE LOGIC CIRCUIT AND LATCHING CIRCUIT
Document Type and Number:
Japanese Patent JP3471628
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a rewritable logic circuit which uses not a transfer gate switch, but a reconstitutable wiring logic element.
SOLUTION: Cells 1 are connected through signal paths Pw, Pn, Pe, and Ps, and have rewritable logic memories Mw, Mn, Me, and Ms having a tristate output function, set the signal paths for input or output, when the tristate output function is set, and read previously stored values out of the logic memory by accessing the memory by using as addresses values inputted through the signal path set for input, thereby outputting them to the signal path set for output.
Inventors:
Kiyoshi Oguri
Hideyuki Ito
Ryusuke Konishi
Kenji Ishii
Hideyuki Ito
Ryusuke Konishi
Kenji Ishii
Application Number:
JP23979498A
Publication Date:
December 02, 2003
Filing Date:
August 26, 1998
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F7/501; H03K3/037; H03K19/177; G06F7/50; (IPC1-7): H03K19/177; H03K3/037
Domestic Patent References:
| JP1093422A | ||||
| JP6276086A | ||||
| JP983348A | ||||
| JP200049591A | ||||
| JP11510038A |
Attorney, Agent or Firm:
Tsuneaki Nagao
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