Title:
【発明の名称】書換え可能な不揮発性半導体記憶装置及びその制御方法
Document Type and Number:
Japanese Patent JP3384409
Kind Code:
B2
Abstract:
A semiconductor non-volatile memory device, having a normal operating mode and a test mode, has bit lines (BL0, BL1, BLr), word lines (X0, X1, Xi) which intersect said bit lines, and a plurality of non-volatile memory cells (Q00, Q10, to Q1i) connected to the bit lines and word lines where the bit lines and word lines intersect. The device also has a supply line (GND) for supplying at least one predetermined potential to all of the memory cells. Means (Qf) are provided for electrically isolating said memory cells from the supply line responsive to a control signal (Gf), these isolating means including a switch circuit (Qf) which is turned on to supply said predetermined potential to the memory cells commonly during the normal operating mode, the switch circuit being turned off during the test mode to isolate the supply line from the memory cells.
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Inventors:
Nobuaki Takashina
Takao Akaogi
Takao Akaogi
Application Number:
JP29070489A
Publication Date:
March 10, 2003
Filing Date:
November 08, 1989
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C29/00; G11C16/12; G11C16/30; G11C16/34; G11C29/06; G11C29/34; G11C29/50; (IPC1-7): G11C29/00; G11C16/06; G11C29/00
Domestic Patent References:
| JP62275399A |
Attorney, Agent or Firm:
Fumihiro Hasegawa (1 person outside)