To provide a ring bus multiprocessor which has more flexibility and is capable of high speed data transfer.
The transfer instruction issued in a processor node 1-1 is selected by the selector node 2-1 to which the instruction reaches first and is sent to a poststage. In other selector nodes 2-2 to 2-8, the inputs from bypass connection lines 3-2 to 3-8 are selected and are sent to the poststage. The same transfer instruction which reaches the selector nodes 2-2 to 2-8 later is recognized as the same instruction is rejected by the comparison of the message ID and the contents of the message ID register in the interior where the message ID of the transfer instruction transferred previous time is stored. The transfer instruction returning after making a round is rejected in the processor node 1-1 issuing the instruction and the selector node 2-1 where the instruction reaches first.
KUROISHI NORIHIKO
KAWACHI KENICHI
MIYAGAWA NOBUAKI
AIHARA REIJI
KOYANAGI MITSUMASA
