Title:
RING OSCILLATOR AND PLL CIRCUIT
Document Type and Number:
Japanese Patent JP3564855
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a ring oscillator suitable as a digital oscillator and a digital phase locked loop(PLL) circuit using the oscillator.
SOLUTION: An oscillating frequency in a loop consisting of logic inversion means is made variable by controlling variably number of the logic inversion stage included in the loop in the ring oscillator making up of the loop of the logic inversion means. In the PLL circuit where a frequency of a signal outputted from a frequency variable oscillation circuit section 10 is controlled in response to phase error information of the input signal, the ring oscillator configured as above is employed for the frequency variable oscillation circuit section 10. That is, the oscillated frequency is made variable by applying switching control of a selection point of a selection means 1 in response to the phase error information of the input signal to obtain a clock signal synchronously with the input signal.
Inventors:
Shinichi Fukuda
Application Number:
JP6752196A
Publication Date:
September 15, 2004
Filing Date:
February 29, 1996
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03K3/03; H03L7/06; H03L7/099; H03L7/113; (IPC1-7): H03K3/03; H03L7/06
Domestic Patent References:
| JP6232703A | ||||
| JP4083413A | ||||
| JP63211919A | ||||
| JP6232703A | ||||
| JP4083413A | ||||
| JP63211919A |
Attorney, Agent or Firm:
Atsuo Waki
Yasuo Asami
Yasuo Asami
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