Title:
リングレジスタ制御型遅延固定ループ及びその制御方法
Document Type and Number:
Japanese Patent JP4812981
Kind Code:
B2
Abstract:
The present invention related to a ring-resister controlled DLL with fine delay line and a direct skew sensing detector, which is applicable to circuitry for compensating skew between external and internal clocks. The ring-register controlled delay locked loop according to the present invention comprises: a first delay group including a plurality of unit delay elements which are lineally coupled to each other for delaying an input clock signal; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the first delay group.
Inventors:
Lee Hoshi
Application Number:
JP2001245735A
Publication Date:
November 09, 2011
Filing Date:
August 13, 2001
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/407; H03L7/081; G06F1/10; G11C7/22; G11C8/00; G11C11/4076; H03K5/131; H03K5/135; H03L7/089
Domestic Patent References:
| JP2000347765A | ||||
| JP11306759A |
Attorney, Agent or Firm:
Teruichi Hase
Maki Kamiya
Maki Kamiya