PURPOSE: To simultaneously execute the ROM cutting for the share of two addresses, and to reduce a ROM cutting time by attaining an address designation and a data designation respectively independently of a first half ROM area and a last half ROM area.

CONSTITUTION: A first circuit means is provided so that the address designated by a ROM cutting address latch 5 can be the simultaneous designation with the address in a first half ROM area 12 and an address in a last half ROM area 13. Namely, at the output side of the latch 5, a ROM cutting address first half output buffer 17 and a ROM cutting address last half output buffer 18 are provided. As a second circuit means, a ROM cutting data latch 6 and a ROM data reading buffer 7 are mounted two by two for areas 12 and 13, and ROM cutting data supplied from the latch 6 are independently supplied to the simultaneously designated address, respectively. The ROM cutting for two addresses can be simultaneously executed through an address switching multiplexer 19, etc., and the ROM cutting time can be saved to about half.