PURPOSE: To reset a CPU when the interval between adjacent pulses is longer than the set time and to prevent the noises due to oscillations, by providing a triggerable multiplexer having its set time longer than the cycle of a pulse signal of a fixed cycle delivered from a CPU.
CONSTITUTION: A triggerable multiplexer 6 which has its set time TW longer than the cycle C of a pulse signal B of a fixed cycle delivered from a CPU5 is provided to a runaway preventing circuit for CPU. An I/O port of the CPU5 is connected to a trigger terminal T1 and retrigger terminal RT of the multiplexer 6, and a differentiating circuit 9 is connected to an output terminal Q of the multiplexer 6. Then the output of the circuit 9 is connected to the reset terminal R of the CPU5 via OR gates 7 and 8. In addition, a power supply reset pulse A is applied to the external reset terminal ER of the multiplexer 6 as well as to one side of a gate 8. Then the CPU5 is reset by the output D of the gate 8 when the interval between adjacent pulses of a signal A delivered from the CPU5 is longer than the set time TW. Thus the noises generated by oscillations can be prevented.
