Title:
SAFE ACTUATOR AND CONTROL LOGIC CIRCUIT THEREOF
Document Type and Number:
Japanese Patent JPS58127202
Kind Code:
A
Abstract:
1. Security device between a command system (1) for a safety actuator (2) and a logic circuit (3) for commanding said actuator, comprising sequential means (10) for transmission of logic signals emitted by the command system (1) to the logic circuit (3), sequential verification means (11) for supplying release signals for the actuator (2) to the logic circuit (3) in the case of failure in the command system (1) or in the case of failure of the transmission means (10), the transmission of signals between the system (1) and the logic circuit (3) being effected after verification of non-failure of the transmission means (10), the sequential verification means (11) comprising delay means (12) connected between the system (1) and the transmission means (10), and a command timer (13) for the delay means (12), the transmission means (10) supplying logic signals (S1 , ... S8 ) for release of the actuator (2) to the logic circuit in the case of failure of the system (1) if after a predetermined time interval (t2 ) the delay means (12) have not received a resetting signal (R) from system (1), the delay means (12) being constituted by a counter whose output (15) is in a first logic state during a predetermined period (t1 ) corresponding to verification of the non-failure of the system (1) and the transmission means (10), and during transmission of logic signals emitted by the system (1), said output (15) being subsequently in a second logic state during said predetermined time interval (t2 ) corresponding to the time elapsing between the instant (theta 1 ) for shift from the first logic state to the second logic state, on the one hand, and the instant (theta 2 ) where the system (1) supplies said resetting signal (R) to the counter, on the other hand, said predetermined time interval (t2 ) having a duration less than the response time of the logic circuit (3), characterized in that the verification means additionally comprise means (14) for comparing the logic states of the signals emitted by the system (1) and the signals (S1 .... S8 ) issuing from the transmission means (10), whereby the comparison means supply an error signal (ER) to the system (1) in the case of a difference between said signals, while not supplying the resetting signal (R) to the delay means (12), after the predetermined interval of time (t2 ), the transmission means (10) thereby supplying signals for release of the actuator (2) to the logic circuit (3).
Inventors:
JIYAN MARII KORAN
Application Number:
JP17693382A
Publication Date:
July 29, 1983
Filing Date:
October 07, 1982
Export Citation:
Assignee:
FRAMATOME SA
International Classes:
G05B9/02; F15B20/00; G05B23/02; G06F11/00; G06F11/14; G06F11/16; G08C25/00; G21C7/36; G21D3/04; (IPC1-7): F15B20/00; G05B9/02; G05B23/02; G21C7/08
Domestic Patent References:
| JPS52147288A | 1977-12-07 |
Attorney, Agent or Firm:
Yoshio Kawaguchi