To provide a sample-and-hold circuit which prevents the occurrence of output voltage distortion caused by an influence of a charge distribution effect.

The sample-and-hold circuit 300 includes a switch SW1, a capacitor CAP1, and an amplifier 310. The switch SW1 has a 1st terminal to receive an input signal Vin and transmit the input signal Vin to a 2nd terminal of the switch SW1 in a sample period. A 1st terminal of the capacitor CAP1 is coupled to the 2nd terminal of the switch SW1, and a 2nd terminal of the capacitor CAP1 is coupled to a voltage for storing the sampling result of the input signal Vin. The amplifier 310 is coupled to the 2nd terminal of the switch SW1, wherein the amplifier is disabled in the sample period, and the amplifier is enabled to generate an output signal according to the sampling result in the hold period.