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Title:
SAMPLE HOLDING CIRCUIT
Document Type and Number:
Japanese Patent JPH02202720
Kind Code:
A
Abstract:

PURPOSE: To eliminate the influence of the clock feed-through by preparing the 1st - 4th switch circuits which are connected to an input terminal, a reference power terminal, the 1st and 2nd capacities, the output terminal of an operational amplifier, and the inverted input terminal of the operational amplifier via one of both ends of each of those switch circuits.

CONSTITUTION: The output voltage vO and the voltage of an inverted input terminal NN and a forward input terminal NP are used as the inverted voltage vNH and the forward voltage vPH respectively in an output period τO when the switch circuits S1 and S3 are turned off and on respectively. Under such conditions, the electric charges QH1 and QH2 stored in the 1st and 2nd capacitors C1 and C2 of a capacity C are defined as QH1=C(vNH-vO) and QH2=CvPH respectively. At the same time, the QH1 and QH2 are equal to QS1 and QS2 applied with the injected charge QC and defined as QH1=QS1+ QC and QH2=QS2+QC respectively. Therefore vPH=VS+(QC/Q) is satisfied. Furthermore vNH=VS+Vofs+(QC/C) is satisfied for vNH and vPH in terms of the virtual earth. Thus vO=VI is satisfied. Thus the output voltage vO obtained in the period τO is equal to the input voltage VI that is sampled at the end time point of a sampling period. Then the influence of the injected charge due to the offset voltage Vofs or the clock feed-through can be cancelled.


Inventors:
YOTSUYANAGI MICHIO
Application Number:
JP2323689A
Publication Date:
August 10, 1990
Filing Date:
January 31, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F3/05; G11C27/02; H03M1/12; (IPC1-7): G06F3/05; H03M1/12
Domestic Patent References:
JPS6340899B21988-08-15
JPS639100A1988-01-14
JP56501223Y
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)