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Title:
SAMPLE AND HOLDING CIRCUIT
Document Type and Number:
Japanese Patent JPS61194700
Kind Code:
A
Abstract:

PURPOSE: To eliminate a loss due to parasitic capacity by providing the 2nd capacitor connected in parallel to the 1st capacitor, an operational amplifier, and the 3rd kind of switch.

CONSTITUTION: There are an input terminal 1, the 1st capacitor C1, the operational amplifier A1, the 1st kind of the 1st switch SW1 connected between the input terminal 1 and one terminal of the capacitor C1, the 1st kind of the 2nd switch SW2 connected between the other terminal of the capacitor C1 and an earth terminal, and the 2nd kind of the 1st switch SW3 which is connected between the other terminal of the capacitor C1 and the inverted input terminal of the operational amplifier A1 and turns on and off reversely of the 1st kind of switch. Further, the 2nd kind of the 2nd switch SW4 is connected between one terminal of the capacitor C1 and earth terminal, the 3rd kind of switch SWD is connected between the inverted input terminal of the operational amplifier A1 and an output terminal 2 and turns on during the on period of the 2nd kind of switch, and the 2nd capacitor CH is connected in parallel to the 3rd kind of switch SWD.


Inventors:
YASUDA SUSUMU
Application Number:
JP3380985A
Publication Date:
August 29, 1986
Filing Date:
February 22, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K7/02; G11C27/02; (IPC1-7): G11C27/02; H03K7/02
Attorney, Agent or Firm:
Uchihara Shin



 
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