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Title:
SAMPLE HOLDING CIRCUIT
Document Type and Number:
Japanese Patent JPS61206999
Kind Code:
A
Abstract:

PURPOSE: To improve a dynamic range and prevent the appearance of the change of an input signal in a hold output signal by making the dynamic range of the signal determined by amplitude of the controlling signal that makes the second transistor conductive or non-conducive.

CONSTITUTION: In a sample holding circuit that makes holding action reverse biasing between the emitter base of a sampling transistor 6, input signals are supplied to the base of the first transistor 15 out of the first and second transistors 15 and 16 in which emitters are connected to each other. At the same time, a controlling signal that makes the second transistor 16 non- conductive during sampling and makes the second transistor 16 conductive during holding is supplied to the base of the second transistor 16. Connecting point of respective emitter of the first and second transistors 15 and 16 is connected to the base of the sampling transistor 6. Thus, the dynamic range is determined by amplitude of controlling signals that make the second transistor 16 conductive or non-conductive.


Inventors:
SASE MASATOSHI
Application Number:
JP4598385A
Publication Date:
September 13, 1986
Filing Date:
March 08, 1985
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C27/02; G05B21/02; H03K7/02; (IPC1-7): G05B21/02; G11C27/02; H03K7/02
Attorney, Agent or Firm:
Sada Ito



 
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