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Patent Searching and Data


Title:
SAMPLE HOLDING CIRCUIT
Document Type and Number:
Japanese Patent JPS6325897
Kind Code:
A
Abstract:

PURPOSE: To minimize an off-setting voltage and to remarkably decrease an output voltage change in a sample holding action by balancing the channel of a signal.

CONSTITUTION: The circuit is composed of two pairs of balance type differential amplifiers A1 and A2 having a differential input terminal and a differential output terminal, switches SN and SP, pairs R1N and R1P of a first resistor having an equal resistance value R1, pairs R2N and R2P of a second resistor having an equal resistance value RF and capacitors CN and CP having an equal capacity Cc. Here, when the switches SN and SP are opened and the voltage holding mode is obtained, the circuit comes to be of a differential form, and therefore, the voltage reducing speed of nodal points 7 and 8 is approximately equal. The change, which is the same phase change voltage of the differential amplifier A2, can be decreased by the order of the same phase removing ratio of A2.


Inventors:
YUGAWA AKIRA
Application Number:
JP16960686A
Publication Date:
February 03, 1988
Filing Date:
July 17, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K7/02; G11C27/02; (IPC1-7): G11C27/02; H03K7/02
Domestic Patent References:
JPS6057600A1985-04-03
Attorney, Agent or Firm:
Ozeki Shinsuke