Title:
SAMPLED ANALOG ELECTRIC SIGNAL PROCESSING CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH01202012
Kind Code:
A
Abstract:
PURPOSE: To obtain a low-voltage current mirror device which has high output impedance by guaranteeing the dynamic adaption of a signal level by a bias voltage. CONSTITUTION: A low-voltage cascode current mirror circuit device is included which has an input branch with 1st and 2nd FETs (T1, T3) and an output branch with 3rd and 4th FETs (T2, T4). To apply a correct bias potential Vt +2Von to the gate electrodes of the 2nd and 4th FETs (T3, T4), a 2nd output branch equipped with other two FETs (T5, T6) and another current mirror circuit equipped with FETs (T7, T8) pass a current through a diode-connected FET (T9), and consequently they generates a voltage Vt +Von . When this current is equal to an input current, the diode-connected FET (T9) is so constituted as to have a gate width-to-length ratio a quarter as large as that of the cascade- connected transistors T3 and T4. This current mirror circuit is built in a current scaling circuit and a current memory circuit for signal current operation.
Inventors:
JIYON BARII HIYUUZU
JIYAN KUREIGU MAKUBESU
JIYAN KUREIGU MAKUBESU
Application Number:
JP32220588A
Publication Date:
August 15, 1989
Filing Date:
December 22, 1988
Export Citation:
Assignee:
PHILIPS NV
International Classes:
G11C27/02; H03H19/00; (IPC1-7): H03H19/00
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)