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Patent Searching and Data


Title:
SAMPLING CIRCUIT
Document Type and Number:
Japanese Patent JPS61263322
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for increase in the dynamic range of an operational amplifier by fetching an input signal in a short time interval to detect the level difference, using a level difference to apply interpolation integration thereby eliminating a switching noise in the input signal.

CONSTITUTION: An input signal Vin is sampled at a sample-and-hold circuit 1 by using sampling clocks s1, s2 and held. The signal sampled by the circuit 1 is subject to operation of level difference ΔV by a difference detection circuit 2. Then an interpolation integration circuit 3 uses the level difference ΔV to apply interpolation integration and its output signal is fed to an A/D conversion circuit 4. The level difference of input signals at two points is detected to apply A/D conversion, then switching noise by sampling switch is cancelled to apply highly accurate A/D conversion.


Inventors:
NAGAYAMA YOSHIHARU
YASUNARI KENJIRO
Application Number:
JP10372985A
Publication Date:
November 21, 1986
Filing Date:
May 17, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03M1/12; (IPC1-7): H03M1/12
Attorney, Agent or Firm:
Katsuo Ogawa