Title:
SAMPLING METHOD FOR SERIAL DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JPH0888624
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method for sampling serial digital signals over a wide allowable range of clock accuracy. SOLUTION: A sampling method for serial digital signals includes phase synchronization of a digital signal D with a clock signal C and sampling of the digital signal at a delay timing Si. The phase synchronization is constituted by determining a timing Pi in a synchronizing test with the sampling timing Si as a reference in order to verify whether the transient interval of the digital signal is advanced to or delayed from the timing of the synchronizing test with the sampling timing as a reference. When (k) is defined as a positive odd number except for '0' and R is defined as a repetition cycle of bits in the digital signal D, the timing of the synchronizing test is determined by adding a complementary delay Y=kR/2 to every sampling timing.
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Inventors:
ROORAN MARUBO
JIYANNKUROODO RU BIAN
ANDORIYU KOFURE
ANNU PIEERU DOUPURUSHI
PASUKARU KUTOO
RUZA NUZAMUZADOUUMOOSABI
JIYANNKUROODO RU BIAN
ANDORIYU KOFURE
ANNU PIEERU DOUPURUSHI
PASUKARU KUTOO
RUZA NUZAMUZADOUUMOOSABI
Application Number:
JP19673995A
Publication Date:
April 02, 1996
Filing Date:
August 01, 1995
Export Citation:
Assignee:
BULL SA
International Classes:
H04L7/00; H04L7/033; (IPC1-7): H04L7/00
Domestic Patent References:
| JPH01162441A | 1989-06-26 |
Attorney, Agent or Firm:
Yoshio Kawaguchi (2 outside)