To provide a sampling conversion device capable of sampling-converting input data and outputting the resulting data, so as to be in synchronism with the clock that has a frequency different from that of an input clock, and reducing the error of output sample data.

A sampling speed conversion device 5 outputs sample data which is inputted, in synchronism with a first clock with a second clock of the frequency different from that of the first clock and comprises an encoder 55, which converts an storage address generated by counting a specified clock into a gray code, a decoder 56, which obtains the output of the encoder 55, in synchronism with the second clock and converts it into a binary code for generating the storage address; and an FIR filter 57 which calculates and outputs the interpolation data of the sample data with a specific interpolation coefficient group read out from a storage part 53 with the output value of the decoder 56 as an address, in synchronism with the second clock, as the filter coefficient.