PURPOSE: To eliminate an idle time slot by converting a high speed address data generated by a pattern generating circuit and a high speed address data generated by a low speed address multiplexer circuit into an address data.

CONSTITUTION: A low speed address multiplexer circuit 5 consists of ksets of low speed address pattern generating circuits 8 and multiplexes k-sets of low speed address data inputted via k-lines of low speed address data lines 106 into one high speed address data. The high speed address data is inputted to an address edit circuit 3a. The circuit 3a edits the high speed address data generated by a high speed address pattern generating circuit 7 and the high speed address data inputted via a data line 105a and outputs the result to a multiplex address data line 104a. As a result, a data read by an output data bus 103a of an information data memory circuit 1 is only the high speed data and an idle time slot on the bus 103 is eliminated. The processing is similar to the case above when the data multiplexer circuit 5 is connected to an address data edit circuit 3b.