Title:
SCALER CIRCUIT
Document Type and Number:
Japanese Patent JP3023434
Kind Code:
B2
Abstract:
PURPOSE: To obtain a circuit in which variable level adjustment is executed with high accuracy and the effect of offset is cancelled by executing multiplication based on the ratio of an input capacitance to a 1st stage feedback capacitance and cancelling an offset of a 1st stage inverter and an offset of a 2nd stage inverter.
CONSTITUTION: A 1st stage coupling capacitor CPO1, a 1st stage inverter INV1, a 2nd stage coupling capacitor CPO2, a 2nd stage inverter INV2 are connected in series and an input voltage Vin is given to the 1st stage coupling capacitor CPO1. Plural feedback paths L21-L24 feeding back its input to an output are connected to the 1st stage inverter INV1 and capacitors C21-C24 are provided in the feedback paths L21-L24. Then the multiplication is executed based on the ratio of the input capacitors C11-C14 to the 1st stage feedback capacitors C21-C24 and an offset by the 1st stage inverter INV1 and that of the 2nd stage inverter INV2 are cancelled.
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Inventors:
Kotobuki Guoliang
Yang Yasuyasu
Nao Takatori
Makoto Yamamoto
Yang Yasuyasu
Nao Takatori
Makoto Yamamoto
Application Number:
JP4204893A
Publication Date:
March 21, 2000
Filing Date:
February 05, 1993
Export Citation:
Assignee:
Takayama Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
G06G7/12; G06G7/14; G06J1/00; H03F3/34; H03G1/00; H03G3/00; H03G3/10; (IPC1-7): G06G7/16
Domestic Patent References:
| JP5457850A | ||||
| JP57159105A | ||||
| JP5840686A | ||||
| JP6041804A | ||||
| JP60260222A | ||||
| JP61229710A | ||||
| JP6221317A | ||||
| JP270115A | ||||
| JP3167699A | ||||
| JP3250911A | ||||
| JP4176204A | ||||
| JP6119472A | ||||
| JP6131479A | ||||
| JP6162230A | ||||
| JP6195483A | ||||
| JP6231286A |
Other References:
【文献】米国特許4446438(US,A)
【文献】米国特許4754226(US,A)
【文献】米国特許4873661(US,A)
【文献】米国特許4893088(US,A)
【文献】米国特許4754226(US,A)
【文献】米国特許4873661(US,A)
【文献】米国特許4893088(US,A)
Attorney, Agent or Firm:
Makoto Yamamoto