PURPOSE: To reduce the load of an operator by forming a patting bit corresponding to data to be scanned in and storing the formed bit in a prescribed register specified by an address memory.

CONSTITUTION: The M-th group of scan-in data m1...mn consisting of m bits are stored in a data memory 2, transferred addresses Am1WAmn for the data m1...mn and a parity bit address PAm for the scan-in data m1...mn are stored in an address memory 1 and an address for scanning-in the parity bit, a parity indicating bit (a) and a bit (b) specifying an even parity or an odd parity are stored in the address PAm. An exclusive OR between the initial read data m1 and the contents of a parity register 6 is found out by an exclusive OR circuit 8 and stored in the register 6 and similar processing is repeated up to the data mn. In the address PAm, the contents of the register up to the data mn. In the address PAm, the contents of the register 6 are sent on the basis of the specification of the bit (b) at the time of the even parity, and at the odd parity, the contents are inverted and sent to generate parities automatically.