Title:
SCAN-PATH SYSTEM SEQUENCE CIRCUIT
Document Type and Number:
Japanese Patent JPH02194375
Kind Code:
A
Abstract:
PURPOSE: To easily diagnose a faulty flip-flop by inputting test data from a scan-in terminal and observing the exclusive OR of all outputs of N flip-flops on a scan path.
CONSTITUTION: The scan-path system sequence circuit 1 outputs a signal which is inputted to a scan-in terminal 2 to a scan-out terminal 4 through N series- connected flip-flops 3-1 to 3-N. Exclusive OR circuits 5-1 to (5-N-1) OR all outputs of the N flip-flops 3-1 to 3-N exclusively and the result is outputted from the circuit 5-N-1. Here, an exclusive OR output terminal 6 receives the output of the circuit 5-N-1 and outputs the exclusive OR as to all the outputs of the N flip-flops 3-1 to 3-N.
Inventors:
SHIMONO TAKESHI
Application Number:
JP1430789A
Publication Date:
July 31, 1990
Filing Date:
January 23, 1989
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F11/22; G01R31/28; (IPC1-7): G01R31/28; G06F11/22
Domestic Patent References:
| JPS6070598A | 1985-04-22 | |||
| JPH0210178A | 1990-01-12 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)