PURPOSE: To prevent potential data at points in a circuit to be detected from being missed during interruption by ignoring software to send a select signal by a CPU and detecting potential data.

CONSTITUTION: A CPU 16 is provided which is connected to rows or columns of a circuit 24 to be detected and succesively sends the select signal to a selecting part 22 at a certain timing independently of software at the time of input of an access signal from access signal generating parts 18 and 20 and reads in potential data at each point included in the row or the column selected by the selecting part 22. Since the CPU 16 ignores software to send the select signal to the selecting part 22 by the access signal and can detect potential data, detection is not interrupted though interrupt is caused. Potential data in one preceding cycle and that of next one cycle are stored in a storage part 30, and they are compared with each other to detect the point where potential data is changed. Thus, misdetection of the change of potential data at points in the circuit 24 to be detected is prevented.