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Title:
SCANNING PATH CONTROLLER
Document Type and Number:
Japanese Patent JPS59110097
Kind Code:
A
Abstract:

PURPOSE: To control a scanning path when storage elements equipped with plural kinds of scanning function coexit on the same scanning path by providing an address counter stepping control circuit for adjusting the value of a scanning adress counter before data is scanned in.

CONSTITUTION: The state of a scanning path controller 12 is set before scanning- in operation to set an address register 17 to "0" and store scan-in data (a), (b), (c), (d), (e), and (f) in a buffer circuit 13. Two clock supply indications 151 from a dummy clock control circuit 15 are supplied to a clock supplying circuit 16, which suplies two clocks 161 to a scanning unit 9. Actual scanning-in operation starts with the succeeding 3rd clock. Namely, a scan clock control circuit 14 indicates the clock supply to the clock supplying circuit 16 through a signal line 141 and updates the contents of the address register 17 through a signal line 142 at the same time, and the buffer circuit 13 outputs the scan-in data to a scan-in data input terminal SI.


Inventors:
MORIYAMA SHIYUUKICHI
Application Number:
JP21701682A
Publication Date:
June 25, 1984
Filing Date:
December 13, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F12/16; G06F11/22; G06F11/267; H01L21/822; H01L27/04; (IPC1-7): G06F11/22; G11C29/00
Attorney, Agent or Firm:
Ashida Tan