Title:
SCHEDULING CIRCUIT
Document Type and Number:
Japanese Patent JP3514215
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a scheduling circuit that eliminates a cell loss caused in a conventional scheduling circuit to the utmost and can transfer an IP packet with high reliability.
SOLUTION: The scheduling circuit consists of an IP scheduling section/ format conversion section 11 that includes a packet FIFO 111, conducts IP scheduling of a received IP packet and converts the IP packet into an ATM cell, cell FIFO sets 12 connected to an output of the section 11, and an ATM scheduling section 13 that applies ATM scheduling to an output in the unit of cells outputted from the cell FIFO sets 12.
Inventors:
Saito, Takashi
Application Number:
JP2000154718A
Publication Date:
March 31, 2004
Filing Date:
May 25, 2000
Export Citation:
Assignee:
NEC CORP
International Classes:
H04J3/26; H04L12/66; H04L47/20; H04L47/22; H04L47/32; H04L47/80; H04Q11/04; (IPC1-7): H04L12/56
Other References:
１９９９年電子情報通信学会総合大会Ｂ−８−１２
Attorney, Agent or Firm:
福山 正博
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