Title:
SCRAMBLE DECIDING CIRCUIT AND AUDIO DATA DECODER OF SATELLITE BROADCASTING RECEIVER
Document Type and Number:
Japanese Patent JP2622065
Kind Code:
B2
Abstract:
PURPOSE: To decide the existence of scramble and to mute audio data at the time of decoding audio data that is received by a satellite broadcasting receiver.
CONSTITUTION: This device consists of a circuit 310, which receives frame data that has a large number of PCM audio data channels, successively performs detection 313 of the logic state of a pay flag that is included each channel data, performs gating 315 together and generates pay flag data of each channel in a frame cycle, a circuit 330 which receives a clock of a frame cycle, makes counting BC1 and generates a multiple frame signal of a prescribed frame cycle and a majority deciding circuit 350 which receives the pay flag data and a multiple frame signal, accumulates 351 of the pay flag data in a cycle of the multiple frame signal, decides 352 as a scramble at the time of a prescribed number or more and generates an audio mute signal.
Inventors:
Hiroshi Han
Application Number:
JP9978493A
Publication Date:
June 18, 1997
Filing Date:
April 26, 1993
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H04H1/00; H04H60/15; H04K1/00; H04L1/00; H04N7/16; H04N7/20; H04N21/435; H04N21/439; (IPC1-7): H04N7/16; H04N7/20
Domestic Patent References:
| JP647882A |
Attorney, Agent or Firm:
Yasunori Otsuka (1 person outside)
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