Title:
SEALING METHOD FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5815257
Kind Code:
A
Abstract:
PURPOSE: To improve the sealability and the electric characteristics of an integrated circuit by coating an adhesive on the sealed part of a hollow package and then defoaming it under reduced pressure.
CONSTITUTION: A substrate 3 and a cover 4 formed of synthetic resin are bonded with a liquid epoxy resin adhesive 5 at an ambient temperature, and a transistor chip 1 is sealed in the hollow package. Then, a hollow package is stationarily placed in a pressure resistant container, which is evacuated via a vacuum pump to be reduced to 150mmHg. Then, the operations to return to the normal pressure are repeated twice, thereby defoaming the adhesive.
Inventors:
KATOU KAZUO
NAKANO TATSUO
TORIGOE TAKASHI
ASAI SHINICHIROU
NAKANO TATSUO
TORIGOE TAKASHI
ASAI SHINICHIROU
Application Number:
JP11303181A
Publication Date:
January 28, 1983
Filing Date:
July 21, 1981
Export Citation:
Assignee:
DENKI KAGAKU KOGYO KK
International Classes:
C09J5/00; C09J5/06; H01L21/50; H01L23/02; (IPC1-7): C09J5/00; H01L23/02
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