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Title:
SEALING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0274054
Kind Code:
A
Abstract:

PURPOSE: To improve a power efficiency and a sealing property by a method wherein a pulse current is applied directly between a metal cap and a metal ring when they are electrically welded to each other.

CONSTITUTION: An IC is mounted on a ceramic substrate 4 to which a metal ring 3 has been fixed and a metal cap 2 is put on the metal ring 3. Roller electrodes 1 are provided pressing the metal cap 2, a pulse current source 5 is connected between the roller electrodes 1 and the metal ring 3, and a pulse current is made to flow. When the wiring has taken place as mentioned above, the pulse current is made to flow from an electrode of the pulse current source 5 to the other electrode via the roller electrodes 1, the metal cap 2, and the metal ring 3, so that an invalid electrode is eliminated. By this setup, a power efficiency and a sealing property can be improved.


Inventors:
SUGIMOTO MITSUO
Application Number:
JP22575888A
Publication Date:
March 14, 1990
Filing Date:
September 09, 1988
Export Citation:
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Assignee:
KYUSHU NIPPON ELECTRIC
International Classes:
H01L23/02; (IPC1-7): H01L23/02
Domestic Patent References:
JPS6230352A1987-02-09
JPS54155767A1979-12-08
JPS5474374A1979-06-14
JPS5477572A1979-06-21
JPS5421169A1979-02-17
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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