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Patent Searching and Data


Title:
SEALING METHOD OF SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JPS5664456
Kind Code:
A
Abstract:

PURPOSE: To provide 100% of yield in sealing the semiconductor element by sealing a package formed by covering a substrate fixed with a semicnductor element chip thereon through an adhesive with a cover while maintaining the gas pressures at the outside and the inside of the package equal within a jig when pressurizing and heating the package in sealing it.

CONSTITUTION: A glass cover 2 is placed through an epoxy resin adhesive 3 on the peripheral edge to cover the semiconductor element chip on a substrate 1 made of ceramic or the like fixed with the chip already. Then, the surface of the cover 2 and the back surface of the substrate 1 are interposed with a spring 4, is heated to cure the adhesive 3 in sealing the chip. At this time the following steps are conducted. That is, the substrate 1 is inserted into the space in the jig made of upper and lower flanges 5 and 6, the flanges 5 and 6 are tightened through a copper packing 7 by a bolt 8, are heated at predetermined temperature while measuring the temperature of the flanges 5 and 6. Thus, the flatness of the sealing surface is not necessarily increased, but the sealing can be completed.


Inventors:
FUNAHASHI IKUHEI
INOUE KATSUYUKI
Application Number:
JP14030179A
Publication Date:
June 01, 1981
Filing Date:
October 30, 1979
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L23/02; H01L21/56; (IPC1-7): H01L23/02