Title:
安全なプログラミング可能論理装置
Document Type and Number:
Japanese Patent JP2004505534
Kind Code:
A
Abstract:
A programmable logic chip and configuration memory chip are mounted within a multi-chip module to form a single package. The configuration memory has a security bit which in a first state allows programming and read-back of configuration data in the memory chip via external pins of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.
More Like This:
| JP2001034468 | SECURITY SYSTEM |
| WO/2003/058410 | USAGE PERIOD MANAGEMENT SYSTEM FOR APPLICATIONS |
| JP6917150 | Code protection methods and computer programs |
Inventors:
Mason, Martin Tee
Cunnari, Nancy Di
Kuo, Harry H
Cunnari, Nancy Di
Kuo, Harry H
Application Number:
JP2002515705A
Publication Date:
February 19, 2004
Filing Date:
June 11, 2001
Export Citation:
Assignee:
ATMEL CORPORATION
International Classes:
G06F21/12; G06F12/14; G06F21/10; G06F21/14; H03K19/173; H03K19/177; H04L9/10; (IPC1-7): H03K19/173; G06F1/00
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai