Title:
SELECTING CIRCUIT FOR BIT LINE PAIR OF SRAM MEMORY CELL ARRAY
Document Type and Number:
Japanese Patent JP3297745
Kind Code:
B2
Abstract:
PURPOSE: To correctly select a bit line pair by controlling switching of any one bit line pair by means of a logical operation with pairs of bit line selecting signals, LSB signals of a lower address and their inverted signals.
CONSTITUTION: Column addresses Y1-Yn of (n) pieces converted to bit line pair selecting signals C1-C2n of 2n bit line pairs by the column decoder 11. Single column switches 1a, 1b are respectively connected to each bit line of both ends of a memory cell array, pairs of column switches for Bo pair and Be pair 2e1, 2e2,...2o1, 2o2... which are composed of pairs of switches connected in parallel are respectively connected to the other bit lines. On the other hand, a logical product is obtained by means of signals C1-C2n, LSB signals of lower address and inverted signals, and selection of each bit line pairs can be correctly performed by using their output signals as control signals for selecting Bo pair or Be pair.
Inventors:
Tsutomu Ichikawa
Application Number:
JP4788492A
Publication Date:
July 02, 2002
Filing Date:
February 04, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11C11/413; G11C11/41; G11C11/412; G11C11/418; (IPC1-7): G11C11/41; G11C11/412; G11C11/418
Domestic Patent References:
| JP1178199A | ||||
| JP5136372A |
Attorney, Agent or Firm:
Kuninori Funabashi