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Title:
SELF-RESTORING SYSTEM OF RING COUNTER
Document Type and Number:
Japanese Patent JPS58142632
Kind Code:
A
Abstract:

PURPOSE: To self-restore a malfunction, by providing a resetting circuit of a clock pulse, and shaping the clock pulse width within a prescribed value.

CONSTITUTION: A CLOCK signal is applied to FFs 4', 6' and 8', and also an opposite phase signal of the CLOCK signal is applied to FFs 3', 5' and 7'. Accordingly, the FFs 3'∼8' are triggered alternately, and clock pulses T0∼T5 are outputted repeatedly. Subsequently, a resetting circuit 9 for self-correction sets the FF 3' for generating the clock pulse T0, by rise of the clock pulse T2, and in the same way, the FFs 4'∼8' are set by rise of T3∼T5, T0 and T1, respectively. By constituting in this way, for instance, even if pulse width of the clock pulse T2 becomes large due to a malfunction, it is reset by rise of the clock pulse T4, therefore, the self-restoration can be executed without transferring the malfunction to the following clock pulse.


Inventors:
MUTOU KOUJI
TAKANO MASAHIRO
Application Number:
JP2437782A
Publication Date:
August 24, 1983
Filing Date:
February 19, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K21/40; H03K23/54; (IPC1-7): H03K23/04
Attorney, Agent or Firm:
Toshiyuki Usuda



 
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