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Title:
SELF-SYNCHRONIZING TYPE ANALOG CIPHER SYNCHRONIZING SYSTEM
Document Type and Number:
Japanese Patent JPS61146027
Kind Code:
A
Abstract:

PURPOSE: To secure a cipher synchronization even after communication has been suspended, by feeding back a part of an output code of a block cipher device of a transmitting device to an input code, and also transmitting it to a reception side, in a communication system for executing an encipherment by a transposition of a frequency spectrum.

CONSTITUTION: A high speed Fourier converting part 19 converts an input signal to a frequency spectrum at every prescribed frame, and inputs it to a transposing part 10. A block cipher device 15 enciphers by a key K an input code which has been set in advance in an initial vector register (IVR)16, and sets an output code to an output register 17. By an output of the register 17, the transposing part 10 is controlled, and a part of the output of the register 17 is fed back to the IVR16. A part of the output of the register and an output of the transposing part 10 are transmitted through a reverse high speed Fourier transformer 12. In a reception side, a signal corresponding to a part of the output of the transmission side is extracted from a high speed Fourier transforming part 33, and supplied to an IVR36.


Inventors:
AKIYAMA RYOTA
YATSUHOSHI AKIMASA
AZUMA MITSUHIRO
TORII NAOYA
Application Number:
JP26920484A
Publication Date:
July 03, 1986
Filing Date:
December 20, 1984
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L1/04; (IPC1-7): H04L1/04
Attorney, Agent or Firm:
Sadaichi Igita