To shorten the develope period of a semi-conductor integrated circuit device, to make circuit performance high and to reduce a cost.
Pads 51a, 51b and 52a which are electrically connected to respective integrated circuits are respectively formed in a RAM substrate 11A, an MPU(microprocessor unit substrate 11B as an LSI core, and an FPGA(field programable gate array) substrate 12 specifying the circuit after packaging. Through the use of technique for adhearing semi-conductor chips, the main surface 11a of the RAM substrate 11A, the main surface 11b of the MPU substrate 11B and the main surface 12a of the FPGA substrate 12 respectively pinch balls 14 consisting of solderirng or steel, etc., in the respective pads 51a, 51b and 52a and facing-connected so that RAM, MPU and FPGA are respectively connected electrically.
TANAKA YASUHIRO
OKAZAKI KAORU
TSUZUKI KATSUO
KIMURA FUMIHIRO
